This invention relates to an information processing system and a method of processing suitable for speeding up the invalidation process for the address transformation buffer.
Simulated computer systems for realizing simultaneous operations of a plurality of operating systems in a single computer system are called "Virtual Machines (VMs)". In contrast to virtual machines, an actual computer is called a "Real Machine". The virtual machines are created through the distribution of resources of the real machine by a virtual machine control program and the simulation by the real machine, so that operating systems are run under the respective virtual machines. Use of this computer ability enables a single real computer system to perform simultaneous, parallel operations of a plurality of operating systems.
In realizing such a virtual computer system with a computer system having a virtual storage system, there exist addresses of three levels as follows.
Level 1: Real address of main memory (real address for the real machine) PA1 Level 2: Virtual address for the real machine (real address for a virtual machine) PA1 Level 3: Virtual address for a virtual machine
Generally, a computer with the virtual storage system incorporates a translation lookaside buffer (TLB) in the processor and stores pairs of virtual address and corresponding real address, so that address conversion is implemented in a short time. In the virtual storage system of a virtual computer system, the TLB has a record of pairs of level-3 address and level-1 address, and it is used to carry out 2-stage address conversion from level 3 to level 2 then from level 2 to level 1, which is inherently required of the virtual computer system.
Japanese Patent Kokai (Laid-Open) Nos. 53-101234 and 54-34723 disclose such a virtual computer system, which is provided in TLB entries with pairs of level-3 address and level-1 address, virtual machine identifiers (VMIDs), and VALID bits. The purpose of having a VMID in TLB is to distinguish level-3 addresses of different virtual machines by the TLB.
In the virtual computer system, the TLB invalidation process for a running VM is implemented by resetting the VALID bit of the TLB entry having a VMID equal to the VMID held in the VMID register. Among TLB entries, the entry having a relevant VMID is searched, and its VALID bit is reset.
Japanese Patent Kokai (Laid-Open) No. 60-57449 discloses a virtual computer system, in which is provided a VMID stack for registering a plurality of VMIDs, with the TLB being designed to hold information indicative of the position in the VMID stack (VM stack number) in place of VMID. The system of the above patent publication is intended to avoid the increase in the number of bits of the VMID field in the TLB in the case of increased VM multiplexing. The VM stack number has less number of bits than VMID, and the correspondence between the VM stack number and VMID is retained in the VMID stack. However, the above patent reference does not disclose the total purging of TLB entries pertinent to a running VM.
Current computer systems require an improved address translation technology that overcomes these problems and others and to provide an address translation process that is advanced in purge processing.